The prior art teaches the formation of integrated circuits which utilize one or more FinFET type field effect transistors. The FinFET transistor comprises a channel region which is oriented to conduct an electrical current parallel to the surface of the substrate. The channel region is provided in an elongated section of semiconductor material. The source and drain regions of the transistor are formed in the elongated section on either side of the channel region. A gate is placed over and on both opposed sides of the elongated section at the location of the channel region to provide for control over the conductive state of the transistor. This FinFET design is well suited for manufacturing a multi-channel transistor in which multiple elongated sections are formed in parallel to define neighboring channel regions which are separated from each other by an intermediate gate portion of the transistor gate spanning with a perpendicular orientation over the multiple elongated sections.
A FinFET transistor is created from at least one thin portion (referred to as the “fin”) of semiconductor material defining the elongated section which is used to form the channel of the transistor and also its source and drain zones. This fin is typically defined by a mask that is formed on top of a monocrystalline silicon (or other semiconductor material, such as silicon-germanium) at the position of the fin. The substrate material is then directionally etched where there is no mask, to a determined depth, such that the elongated section defining the fin remains under the mask and is composed of the substrate material.
In one prior art implementation, the fin of semiconductor material which is thus obtained, and which comprises the channel of the final transistor, is not electrically insulated from the active portion of the circuit substrate, which itself is also of crystalline semiconductor material. Such a FinFET device suffers from three distinct types of leakage current. A first type of leakage current can circulate between the source and drain of the FinFET transistor via the active portion of the substrate situated below the channel. This first leakage current, internal to each transistor, is not controlled by the potential applied to the transistor gate. A second type of leakage current arises because the channel of the FinFET transistor is also in electrical contact with the channels of other transistors of the same conductivity type via the substrate. The second leakage current flows between transistors in the form of an inter-transistor leakage current. A third type of leakage current appears between the channel of each FinFET transistor and a lower part of the substrate in response to the substrate being connected to a reference potential.
To address the leakage current issues noted above, procedures for dielectrically isolating the fin are known in the art.
In one technique, referred to as bottom oxidation through STIs (BOTS), shallow trench isolation (STI) structures are formed on either side of the fin. The silicon material of the fin is protected on a top side by a barrier layer (for example, of silicon nitride) and the upper lateral sides of the fin are isolated from the STI structures by another barrier layer (for example, of silicon nitride). The integrated circuit wafer is then subjected to an oxidation process. The barrier layers function as oxygen (O2) barriers and a lower portion of the fin (below the lateral barrier layers) is converted to a thermal oxide material which isolates the upper portion of the fin from the underlying substrate material. This process produces an undesirable scalloped interface shape at the bottom of the fin (due to the nature of the thermal oxide growth). Additionally, the process is not compatible with fins made of silicon-germanium (SiGe), and thus cannot be advantageously used when forming p-channel SiGe FinFET devices.
In another technique, referred to in the art as silicon on nothing (SON), a bottom portion of the fin is formed of silicon-germanium and an upper portion of the fin is formed of silicon. A selective etch is performed to remove the bottom SiGe portion to open a region between the underside of the Si fin and the underlying substrate. A dielectric material filling operation is then performed to fill the opened region with an insulating material. This process presents mechanical stability issues with respect to the Si fin. Additionally, complete fill of the opened region with the insulating material cannot be assured, and any voids that are left present tunnel fill conformality issues.
There is accordingly a need in the art for an improved process to isolate fins from the substrate during FinFET configuration.
As CMOS process technology continues to scale towards smaller and smaller dimensions, further improvement in transistor performance is needed. Those skilled in the art recognize that the use of silicon-germanium (SiGe) materials for transistor fabrication provide for a significant boost in transistor performance, especially with respect to p-channel field effect transistor devices. Indeed, the art is moving towards the use of SiGe for p-channel devices of many different types. Specific to the use of FinFET devices, those skilled in art recognize a need to form the fin of the p-channel device from a SiGe material in order to reach improved transistor performance levels over prior art Si material only devices. Additionally, the SiGe fin must be isolated from the underlying substrate to address, at the very least, concerns over leakage current as described above.
Thus, the need an improved process to isolate fins from the substrate during FinFET configuration includes the need to provide a solution compatible with the formation SiGe structures.